View MB89816A_200441.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

To Top / Lineup / Index
FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12507-2E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89810A Series
MB89816A/P817A
s DESCRIPTION
The MB89810A series is a line of single-chip microcontrollers based on the F2MC*-8L CPU core which can operate at low voltage but at high speed. The microcontrollers contain peripheral function such as timer, serial interface, a UART, and an external interrupt. The MB89810A series is applicable to a wide range of applications from welfare products to industrial equipment, including portable devices. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
High speed processing at low voltage Minimum execution time: 0.8 s/3.0 V, 1.33 s/2.2 V * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
* Four types of timers 8-bit PWM timer: 2 channels (also serve as reload timers) 16-bit timer/counter 21-bit time-base timer * Two serial interface 8-bit synchronous serial (Switchable transfer direction allows communication with various equipment.) UART (5-, 7-, or 8-bit transfer capable)
(Continued)
s PACKAGE
64-pin Plastic QFP
(FPT-64P-M06)
To Top / Lineup / Index
MB89810A Series
(Continued) * External interrupt: 8 channels Eight channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). * Low-power consumption modes Stop mode (Oscillation stops to minimize the current consumption) Sleep mode (The CPU stops to reduce the current consumption to approx. 1/3 of normal)
s PRODUCT LINEUP
Part number Parameter Classification ROM size MB89816A Mass-production product (mask ROM products) 24 K x 8 bits (internal mask ROM) MB89P817A One-time PROM product (for evaluation and development) 32 K x 8 bits (internal PROM, programming with general-purpose EPROM programmer) 2048 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time: Input ports: Output ports: I/O ports (N-ch open-drain): I/O ports (CMOS): Total: 136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.8 s/5 MHz 7.2 s/5 MHz 8 (All also serve as peripherals.) 8 5 (for LED driving) 32 (14 ports also serve as peripherals.) 53
RAM size CPU functions
Ports
8-bit PWM timer
Two internal channels 8-bit reload timer operation (toggled output capable, operating clock cycle: 3 different cycles) 8-bit resolution PWM operation (conversion cycle: 3 different cycles) 16-bit timer operation 16-bit event counter operation 5-, 7-, or 8-bit transfer capable Built-in baud rate generator Clock synchronous/asynchronous data transfer capable 8-bits LSB-first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks) 8 independent channels (edge selection, interrupt vector, source flag) 4 channels: Level detection (level selectable) 4 channels: Edge detection (edge selectable) Used also for wake-up from the stop/sleep mode. (Edge detection is also permitted in stop mode.)
8-bit timer/counter UART
8-bit Serial I/O
External interrupt
(Continued)
2
To Top / Lineup / Index
MB89810A Series
(Continued)
Part number Parameter Watch interrupt Watchdog timer reset Standby mode Process Package Operating voltage 2.2 V to 6.0 V* MB89816A MB89P817A
Interrupt cycles: 4 different cycles (subclock) Reset occurrence cycle: 839 ms/5 MHz Sleep mode, stop mode CMOS FPT-64P-M06 2.7 V to 6.0 V*
* : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.")
s PIN ASSIGNMENT
(Top view) P47/SCL2 P46/RXD2 P45/TXD2 P44/SCL1 P43/RXD1 P42/TXD1 P41/EC VCC P40 P54 P53 P52 P51 P30/PWE P31/SCK P32/SO P33/SI P34/PWO P35/PWI P36/PTO1 P37/PTO2 P60/INT0 P61/INT1 P62/INT2 VCC P63/INT3 P64/INT4 P65/INT5 P66/INT6 P67/INT7 X0A X1A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P50 VSS P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20
RST MOD0 MOD1 X0 X1 VSS P27 P26 P25 P24 P23 P22 P21 (FPT-64P-M06)
3
To Top / Lineup / Index
MB89810A Series
s PIN DESCRIPTION
Pin no. 23 24 18 19 21 22 20 Pin name X0 X1 X0A X1A MOD0 MOD1 RST C B Operating mode selection pins Connect directly these pins directly to VSS. Reset I/O pin This pin is an N-ch open-drain output type with a pull-up resistor and a hysteresis input type. "L" is output from this pin by an internal reset source. The internal circuit is initialized by the input of "L". General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. General-purpose I/O ports A pull-up resistor option is provided. These ports have the port output inverting function. General-purpose output ports These ports have the port output inverting function. General-purpose output ports General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection enable input (PWE). PWE input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O for the 8-bit serial I/O (SCK). SCK input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output for the 8-bit serial I/O (SO). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input for the 8-bit serial I/O (SI). SI input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection output (PWO). General-purpose I/O port A pull-up resistor option is provided. Also serves as a pulse width detection input (PWI). PWI input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 1 (PTO1). I Subclock crystal oscillator pins Circuit type A Main clock oscillator pins Function
49 to 42
P00 to P07
D
41 to 34
P10 to P17
D
33 to 30 29 to 26 1
P20 to P23 P24 to P27 P30 /PWE
F F E
2
P31/SCK
E
3
P32/SO
D
4
P33/SI
E
5
P34/PWO
D
6
P35/PWI
E
7
P36/PTO1
D
(Continued)
4
To Top / Lineup / Index
MB89810A Series
(Continued)
Pin no. 8 Pin name P37/PTO2 Circuit type D Function General-purpose I/O port A pull-up resistor option is provided. Also serves as the toggle output for the 8-bit PWM timer 2 (PTO2). General-purpose I/O port A pull-up resistor option is provided. General-purpose I/O port A pull-up resistor option is provided. Also serves as a 16-bit timer/counter input (EC). EC input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 1 for the UART (TXD1). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 1 for the UART (RXD1). RXD1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 1 for the UART (SCL1). SCL1 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the data output 2 for the UART (TXD2). General-purpose I/O port A pull-up resistor option is provided. Also serves as the data input 2 for the UART (RXD2). RXD2 input is hysteresis input. General-purpose I/O port A pull-up resistor option is provided. Also serves as the clock I/O 2 for the UART (SCL2). SCL2 input is hysteresis input. N-channel open-drain I/O ports A pull-up resistor option is provided only for the MB89816A. General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT0 to INT2). These ports are a hysteresis input type. General-purpose I/O ports A pull-up resistor option is provided. Also serve as an external interrupt input (INT3 to INT7). These ports are a hysteresis input type. Power supply pin Power supply (GND) pin
56 58
P40 P41/EC
D E
59
P42/TXD1
D
60
P43/RXD1
E
61
P44/SCL1
E
62
P45/TXD2
D
63
P46/RXD2
E
64
P47/SCL2
E
51 to 55 9 to 11
P50 to P54 P60/INT0 to P62/INT2
G H
13 to 17
P63/INT3 to P67/INT7
H
12, 57 25, 50
VCC VSS
- -
5
To Top / Lineup / Index
MB89810A Series
s I/O CIRCUIT TYPE
Type A
X1
Circuit
Remarks * Main clock * At an oscillation feedback resistor of approximately 2 M (1 to 5 MHz) * CR oscillator circuit selectability
X0
Standby control signal
B
C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * Hysteresis input
N-ch
D
R P-ch P-ch
* CMOS output * CMOS input
N-ch
* Pull-up resistor optional E
R P-ch P-ch
* CMOS output * CMOS input * Hysteresis input (resource input)
N-ch
* Pull-up resistor optional
(Continued)
6
To Top / Lineup / Index
MB89810A Series
(Continued)
Type F
P-ch
Circuit * CMOS output
Remarks
N-ch
G
R P-ch
* N-ch open-drain output * CMOS input
N-ch
* Pull-up resistor optional (only for the MB89816A) H * Hysteresis input * Pull-up resistor optional
I
X1A X0A
* Subclock (30 to 40 kHz) * At an oscillation feedback resistor of approximately 4.5 M
7
To Top / Lineup / Index
MB89810A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
4. Precautions when Using an External Clock
Even when an external clock is used, oscillation stabilization time is required for power-on reset (optional) and wake-up from stop mode.
8
To Top / Lineup / Index
MB89810A Series
s PROGRAMMING TO THE EPROM ON THE MB89P817A
In EPROM mode, the MB89P817A functions equivalent to the MBM27C256A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. * Writing Procedure (1) Set the EPROM programmer to the MBM27C256A. (2) Load program data into the EPROM programmer at 0007H to 7FFFH (note that addresses 8007H to FFFFH while operating as operating mode assign to 0007H to 7FFFH in EPROM mode). Load option data into addresses 0000H to 0006H of the EPROM programmer. (For information about each corresponding option, see "* Setting OTPROM Option Bit Map.") (3) Program with the EPROM programmer. * Memory Space Memory space is diagrammed below.
0000H Option area
0007H
Program area (PROM)
7FFFH
9
To Top / Lineup / Index
MB89810A Series
* Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM (one-time PROM) microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
* Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. * EPROM Programmer Socket Adapter Package FPT-64P-M06 Compatible socket adapter ROM-64QF-28DP-8L
Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 Note: Connect the jumper pin to VSS when using. Depending on the EPROM programmer, inserting a capacitor of approx. 0.1 F between VPP and VSS or VCC and VSS can stabilize programming operations.
10
To Top / Lineup / Index
MB89810A Series
* OTPROM Option Bit Map Bit 7 Vacancy Bit 6 Vacancy Bit 5 Vacancy Bit 4 Bit 3 Reset pin output 1: Enabled 0: Disabled P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes Bit 2 Bit 1 Bit 0
Single-clock setting 0000H Readable and Readable and Readable and 1: Dual-clock writable writable writable 0: Single-clock P07 Pull-up 0001H 1: No 0: Yes P17 Pull-up 0002H 1: No 0: Yes P37 Pull-up 0003H 1: No 0: Yes P47 Pull-up 0004H 1: No 0: Yes Vacancy P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P36 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes Vacancy P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P35 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes Vacancy P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P34 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes
Power-on Oscillation stabilization time reset 4/FCH 01 214/FCH 1: Enabled 00 217 18 0: Disabled 10 2 /FCH 11 2 /FCH P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P61 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes
P64 Pull-up 0005H Readable and Readable and Readable and 1: No writable writable writable 0: Yes Vacancy Vacancy Vacancy Vacancy
Oscillator type P67 Pull-up 0006H Readable and Readable and Readable and Readable and 1: Crystal 1: No writable writable writable writables 0: CR 0: Yes Note: Each bit defaults to 1.
11
To Top / Lineup / Index
MB89810A Series
s BLOCK DIAGRAM
X0 X1
Main clock oscillator
Time-base timer
Clock controlletr
8-bit PWM timer 2
P37/PTO2
X0A X1A
Subclock oscillator
8-bit PWM timer 1 Port 3
P36/PTO1
RST
Reset circuit (WDT) Internal bus 8-bit serial I/O 1
P31/SCK P33/SI P32/SO
8 P00 to P07 8 P10 to P17 Port 0 and port 1 CMOS I/O port
Pulse width detection
P 3 0 / P WE P 3 5 / P WI P 3 4 / P WO
8 P20 to P27
Port 2 CMOS output port
CMOS I/O port
UART
P44/SCL1 P47/SCL2 P43/RXD1 P46/RXD2 P42/TXD1 P45/TXD2
RAM (2048 x 8 bits)
16-bit timer/counter
Port 4
P41/EC
F2MC-8L CPU
CMOS I/O port
P40
ROM (24 K x 8 bits)
Port 5 N-ch open-drain I/O port
5 P50 to P54
Other pins VCC x 2, VSS x 2 MOD0, MOD1
Input port
12
Port 6
External interrupt
8
8
P60/INT0 to P67/INT7
To Top / Lineup / Index
MB89810A Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89810A series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located at the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89810A series is structured as illustrated below. Memory Space
MB89816A 0000H I/O 0080H 0100H
Register
MB89P817A 0000H I/O 0080H 0100H
Register
0200H RAM 2 KB 0880H
0200H RAM 2 KB 0880H
Not available Not available
8000H Optional PROM 8007H A000H
ROM 24 KB
PROM 32 KB
FFFFH
FFFFH
13
To Top / Lineup / Index
MB89810A Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following dedicated registers are provided:
Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS):
A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status
Initial value FFFDH Undefined Undefined Undefined Undefined Undefined I-flag = 0, IL1, 0 = 11 Other bits are undefined.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.)
Structure of the Program Status Register
15 PS
14
13 RP
12
11
10
9
8
7 H
6 I
5
4
3 N
2 Z
1 V
0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
14
To Top / Lineup / Index
MB89810A Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit.
IL1 0 0 1 1
IL0 0 1 0 1
Interrupt level 1 2 3
High-low High
Low = no interrupt
N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: V-flag: Set when an arithmetic operation results in 0. Cleared otherwise. Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur.
C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction.
15
To Top / Lineup / Index
MB89810A Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit register for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89816A. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
16
To Top / Lineup / Index
MB89810A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) SMR SDR (R/W) (R/W) (R/W) (R/W) PIVE TMCR TCHR TCLR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (W) (R/W) (R) SYCC STBC WDTC TBCR WPCR PDR3 DDR3 PDR4 DDR4 PDR5 PDR6 Read/write (R/W) (W) (R/W) (W) (R/W) Register name PDR0 DDR0 PDR1 DDR1 PDR2 Register description Port 0 data register Port 0 data direction register Port 1 data register Port 1 data direction register Port 2 data register Vacancy Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 data direction register Port 4 data register Port 4 data direction register Port 5 data register Port 6 data register Vacancy Vacancy Vacancy Vacancy Vacancy Port inverting operation enable register 16-bit timer count register 16-bit timer count register (H) 16-bit timer count register (L) Vacancy Serial I/O mode register Serial I/O data register Vacancy Vacancy
(Continued)
17
To Top / Lineup / Index
MB89810A Series
(Continued)
Address 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H to 7AH 7BH 7CH 7DH 7EH 7FH (W) (W) (W) Not available ILR1 ILR2 ILR3 ITR (R/W) (R/W) (R/W) (R/W) (R/W) PWCR EIC1 EIC2 EI2E EI2F (R/W) (R/W) (R/W) (W) (W) CNTR1 CNTR2 CNTR3 COMR2 COMR1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) Register name SMC1 SRC SSD SIDR/SODR SMC2 Register description UART serial I/O mode control register 1 UART serial I/O rate control register UART serial I/O status/data control register UART serial I/O data control register UART serial I/O mode control register 2 Vacancy Vacancy Vacancy PWM timer control register 1 PWM timer control register 2 PWM timer control register 3 PWM timer compare register 2 PWM timer compare register 1 Vacancy Vacancy Pulse width detection control register External interrupt 1 control register 1 External interrupt 1 control register 2 External interrupt 2 enable register External interrupt 2 flag register Vacancy Vacancy Vacancy Interrupt level register 1 Interrupt level register 2 Interrupt level register 3 Interrupt test register
Note: Do not use vacancies.
18
To Top / Lineup / Index
MB89810A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = 0.0 V)
Parameter Power supply voltage Input voltage
Symbol VCC VI1 VI2 VO1 VO2 IOL IOLAV1 IOLAV2
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 7.0 VCC + 0.3 VSS + 7.0 VCC + 0.3 VSS + 7.0 20 4 10 100 40 -20 -4 -50 -20 300 +85 +150
Unit V V V V V mA mA mA mA mA mA mA mA mA mW C C
Remarks
Except P50 to P54 P50 to P54 Except P50 to P54 P50 to P54 Peak value Average value except pins other than P50 to P54 Average value for P50 to P54 Peak value Average value Peak value Average value Peak value Average value
Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature
IOL IOLAV IOH IOHAV IOH IOHAV PD TA Tstg
Precautions: Permanent device damage may occur if the above "Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
19
To Top / Lineup / Index
MB89810A Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Value Min. 2.2* Max. 6.0 6.0 6.0 VCC + 0.3 VCC + 0.3 VSS + 6.0 0.3 VCC 0.2 VCC VSS + 6.0 +85
Unit V V V V V V V V V C
Remarks Normal operation assurance range MB89816A Normal operation assurance range MB89P817A Retains the RAM state in stop mode P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 (with pull-up resistor) RST, MOD0, MOD1, P60 to P67, Pheripheral input for port 3 and port 4 P50 to P54 (without pull-up resistor) P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54 RST, MOD0, MOD1, P60 to P67, Pheripheral input for port 3 and port4 P50 to P54 (without pull-up resistor)
Power supply voltage
VCC
2.7* 1.5
VIH "H" level voltage VIHS VIHS2 VIL "L" level voltage VILS Open-drain output pin application voltage Operating temperature VD TA
0.7 VCC 0.8 VCC 0.8 VCC VSS - 0.3 VSS - 0.3 VSS - 0.3 -40
* : These values vary with the operating frequency. See Figure 1.
6
Operating voltage (V)
5
Operating assurance range
4 3
2 1
2.0 5.0 1.0 3.0 4.0 Main clock operating frequency (MHz) (at an instruction cycle of 4/FCH) Note: The shaded area is assured only for the MB89816A
Figure 1 20
Operating Voltage vs. Main Clock Operating Frequency (for MB89816A)
To Top / Lineup / Index
MB89810A Series
3. DC Characteristics
(VCC = +5.0 V, VSS = 0.0 V, TA = -40C to +85C)
Value Parameter Symbol Pin Condition Min. "H" level output voltage VOH P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOH = -2.0 mA P40 to P47 P00 to P07, P10 to P17, P20 to P27, P30 to P37, IOL = 1.8 mA P40 to P47, P50 to P54 P60 to P67 P50 to P54 RST IOL = 6 mA VCC = 3 V IOL = 4.0 mA 2.4 Typ. -- Max. -- V Unit Remarks
VOL1 "L" level output voltage VOL2 VOL3 Input leakage current (Hi-z output leakage ILI1 current)
--
--
0.4
V
-- --
-- --
0.5 0.4
V V
P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P54, 0.45 V < VI < VCC P60 to P67, MOD0, MOD1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, VI = 0.0 V P50 to P54, P60 to P67, RST FCH = 5 MHz VCC = 5.0 V tinst = 0.8 s FCH = 5 MHz VCC = 3.0 V tinst = 6.4 s VCC FCH = 5 MHz VCC = 5.0 V tinst = 0.8 s FCH = 5 MHz VCC = 3.0 V tinst = 12.8 s FCL = 32.768 kHz VCC = 3.0 V
--
--
5
A
Without pull-up resistor
Pull-up resistance
RPULL
25
50
100
k
With pull-up resistor
-- -- -- --
4 4.8 0.4 1.0
6 7.5 0.6 1.5
mA mA mA mA
MB89816A MB89P817A MB89816A MB89P817A
ICC1
ICC2
Power supply current*
ICCS1
--
1.2
1.8
mA Sleep mode
ICCS2
-- -- --
0.3 50 500
0.5 100 700
mA A A Subclock mode MB89P817A
ICCL
(Continued)
21
To Top / Lineup / Index
MB89810A Series
(Continued)
(VCC = +5.0 V, VSS = 0.0 V, TA = -40C to +85C)
Value Parameter Symbol Pin Condition Min. ICCLS FCL = 32.768 kHz VCC = 3.0 V FCL = 32.768 kHz VCC = 3.0 V VCC -- Typ. 15 Max. 50 A Subclock sleep mode Watch mode Main clock stop mode at dualclock system Subclock stop mode Main clock stop mode at single-clock system Unit Remarks
ICCT Power supply current*
--
--
15
A
ICCH
FCL = 32.768 kHz VCC = 3.0 V
--
--
10
A
Input capacitance CIN
Other than VCC and VSS
f = 1 MHz
--
10
--
pF
* : The measurement conditions of power supply current are as follows: the external clock and TA = +25C.
22
To Top / Lineup / Index
MB89810A Series
4. AC Characteristics
(1) Reset Timing
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RST "L" pulse width
Symbol tZLZH
Condition --
Value Min. 16 tCH Max. --
Unit ns
Remarks
Note: tCH is the cycle time of the main clock.
tZLZH RST 0.2 VCC 0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V 0.2 V
tOFF
0.2 V
0.2 V
VCC
Note that a sudden increase in supply voltage may result in a power-on reset. When increasing the supply voltage during operation, voltage variation should be within twice the intended increment so that the voltage rises as smoothly as possible.
23
To Top / Lineup / Index
MB89810A Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time
Symbol FCH FCL tCH tCL PWH PWL PWHL PWLL tCR tCF
Pin X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0
Condition
Value Min. 1 -- 200 -- Typ. -- 32.768 -- 30.5 -- 15.2 -- Max. 5 -- 1000 -- -- -- 10
Unit MHz kHz ns s ns s ns
Remarks
--
20 -- --
External clock
Input clock pulse width
Input clock rising/falling time
External clock
X0 and X1 Timing and Conditions
tCH PWH tCR 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWL
Main Clock Conditions
When a crystal or ceramic resonator is used
when an external clock is used
X0
X1
X0
X1 Open
When a CR oscillator is used
X0
X1
24
To Top / Lineup / Index
MB89810A Series
X0A and X1A Timings and Conditions
tCL PWHL tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL
Subclock Conditions
When a crystal or ceramic resonator is used
when an external clock is used
X0A
X1A
X0A
X1A Open
(4) Serial I/O Timings
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time
Symbol tSCYC1 tSLOV1 tIVSH1 tSHIX1 tSHSL tSLSH tSLOV2 tIVSH2 tSHIX2
Pin SCK SCK, SO SI, SCK SCK, SI SCK SCK, SO SI, SCK SCK, SI
Condition
Value Min. 2 tinst -200 1/2 tinst 1/2 tinst 1 tinst 1 tinst Max. -- 200 -- -- -- -- 200 -- --
Unit Remarks ns ns ns ns ns ns ns ns ns
Internal shift clock mode
External shift clock mode
0 1/2 tinst 1/2 tinst
* : tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode.
25
To Top / Lineup / Index
MB89810A Series
(5) UART Timings
(VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCL TXDx time Valid RXDx SCLx Serial clock "H" pulse width Serial clock "L" pulse width SCLx TXDx time Valid RXDx SCLx
Symbol tSCYC tSLOV1 tIVSH1 tSHSL tSLSH tSLOV2 tIVSH2
Pin SCL1, SCL2 SCLx, TXDx
Condition
Value Min. 2 tinst -200 1/2 tinst 1/2 tinst 1 tinst 1 tinst Max. -- 200 -- -- -- -- 200 -- --
Unit Remarks ns ns ns ns ns ns ns ns ns
Internal shift RXDx, SCLx clock mode SCL1, RXD2 SCL1, SCL2 SCLx, TXDx RXDx, SCLx SCL1, RXD2 External shift clock mode
SCLx valid RXDx hold time tSHIX1
0 1/2 tinst 1/2 tinst
SCLx valid RXDx hold time tSHIX2 Notes:
* *
tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode. The edge polarity for the SLCx input is assumed when LSEL bit = 0 for SMC2. The polarity is inverted when LSEL = 1.
Internal Shift Clock Mode
tSCYC SCK/SCLx 2.4 V 0.8 V tSLOV1 2.4 V 0.8 V tIVSH1 SI/RXDx 0.8 VCC 0.2 VCC tSHIX1 0.8 VCC 0.2 VCC 0.8 V
SO/TXDx
External Shift Clock Mode
tSLSH SCK/SCLx 0.8 VCC 0.2 VCC 0.2 VCC tSLOV2 SO/TXDx 2.4 V 0.8 V tIVSH2 SI/RXDx 0.8 VCC 0.2 VCC tSHIX2 0.8 VCC 0.2 VCC tSHSL 0.8 VCC
26
To Top / Lineup / Index
MB89810A Series
(6) Peripheral Input Timings
(VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin EC, INT0 to INT7 EC, INT0 to INT7
Condition -- -- --
Value Min. 2 tinst 2 tinst 512 tCL + 200 or 480 tCL + 200 512 tCL + 200 or 480 tCL + 200 Max. -- -- --
Unit Remarks ns ns ns
Peripheral input "H" pulse tILIH width Peripheral input "L" pulse width "H" input pulse width of pulse width detection enable signal "L" input pulse width of pulse width detection enable signal Notes:
* * *
tIHIL tPWEH
PWE tPWEL -- -- ns
tinst represents the minimum instruction execution time. It varies with the selected system clock and operating mode. tCL represents the subclock cycle time. The PWE pulse width value varies with the first divider selection bit of the watch prescaler. The pulse width is "512 tCL + 200" when divide by 16 is selected; or "480 tCL + 200" when divide by 15 is selected.
EC, INT0 to INT7 0.2 VCC
tIHIL 0.8 VCC 0.2 VCC
tILIH 0.8 VCC
tPWEH 0.8 VCC PWE 0.2 VCC 0.2 VCC
tPWEL 0.8 VCC
27
To Top / Lineup / Index
MB89810A Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning
(Continued)
28
To Top / Lineup / Index
MB89810A Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
29
To Top / Lineup / Index
MB89810A Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. *Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
30
To Top / Lineup / Index
MB89810A Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
31
To Top / Lineup / Index
MB89810A Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
32
L PUSHW A SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP A A,ext POPW MOV MOVW CLRI A,PS SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC
H 4 5 6 7 8 9 A B C D E F
0
1
2
3
0
NOP
SWAP
RET
RETI
1 XCH A A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS XCHW XORW ANDW ORW A, T A A A A, T A A A XOR AND OR
MULU
DIVU
A MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
SUBC
A
A
A
s INSTRUCTION MAP
3
RORC
CMPW
ADDCW
SUBCW
A
A
A
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV
CMP
A,dir
A,dir
ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
6 CMP @EP,#d8
CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A A,@IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 CALLV #7 R5 CALLV #6 BLT rel R4 CALLV #5 BGE rel R3 CALLV #4 BZ rel R2 CALLV #3 BNZ rel R1 CALLV #2 BN rel R0 CALLV #1 BP rel CALLV #0 BC rel BNC rel
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8
8
MOV
CMP
A,R0
A,R0
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV
CMP
A,R1
A,R1
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
A
MOV
CMP
A,R2
A,R2
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
B
MOV
CMP
A,R3
A,R3
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
C
MOV
CMP
A,R4
A,R4
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV
CMP
A,R5
A,R5
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
E
MOV
CMP
A,R6
A,R6
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
MB89810A Series
F
MOV
CMP
To Top / Lineup / Index
A,R7
A,R7
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
33
To Top / Lineup / Index
MB89810A Series
s MASK OPTIONS
No. Part number Specifying procedure Pull-up resistors P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P54, P60 to P67 Power-on reset selection With power-on reset Without power-on reset Main clock oscillation (5 MHz) stabilization time selection approx. 218/FCH (approx. 52.4 ms) approx. 217/FCH (approx. 26.2 ms) approx. 214/FCH (approx. 3.2 ms) approx. 24/FCH (approx. 0 ms) Reset pin ouotput selection With reset output Without reset output Selection either single- or dualclock system Single clock Dual clock Main clock oscillator type selection Crystal or ceramic oscillator CR MB89816A Specify when ordering masking MB89P817A Set with EPROM programmer Can be set per pin. (P50 to P54 are available only for without a pull-up resistor.)
1
Specify by pin
2
Selectable
Setting possible
3
Selectable
Setting possible
4
Selectable
Setting possible
5
Selectable
Setting possible
6
Selectable
Setting possible
FCH: Main clock frequency * : The main clock oscillation setting time is generated by dividing the main clock frequency. Note that the oscillation cycle is not stable immediately after oscillation is started. The settling time value in this data sheet should be used as a reference.
s ORDERING INFORMATION
Part number MB89816APF MB89P817APF Package 64-pin Plastic QFP (FPT-64P-M06) Remarks
34
To Top / Lineup / Index
MB89810A Series
s PACKAGE DIMENSIONS
64-pin Plastic QFP (FPT-64P-M06)
24.700.40(.972.016)
51
3.35(.132)MAX
33
20.000.20(.787.008)
0.05(.002)MIN (STAND OFF)
52
32
14.000.20 (.551.008) INDEX
64 20
18.700.40 (.736.016)
12.00(.472) REF
16.300.40 (.642.016)
"A" LEAD No.
1 19
1.00(.0394) TYP
0.400.10 (.016.004)
0.150.05(.006.002) 0.20(.008)
M
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.00(.709)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details of "B" part
0 10 1.200.20 (.047.008)
C
1994 FUJITSU LIMITED F64013S-3C-2
Dimensions in mm (inches)
35
To Top / Lineup / Index
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
24

▲Up To Search▲

Price & Availability of MB89816A

	To Download MB89816A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .